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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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STCF03ITBR bảng dữ liệu(PDF) 16 Page - STMicroelectronics |
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STCF03ITBR bảng dữ liệu(HTML) 16 Page - STMicroelectronics |
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16 / 33 page  Introduction STCF03I 16/33 pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Any change in the SDA line at this time will be interpreted as a control signal. 7.7 Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 7). The peripheral (STCF03I) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed has to generate an acknowledge pulse after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse duration. In this case, the master transmitter can generate the STOP information in order to abort the transfer. Figure 6. Bit transfer Figure 7. Acknowledge on I2C Bus |
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