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STCF03ITBR bảng dữ liệu(PDF) 15 Page - STMicroelectronics

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STCF03ITBR bảng dữ liệu(HTML) 15 Page - STMicroelectronics

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Introduction
STCF03I
15/33
7.4
Data validity
As shown in Figure 4, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
7.5
Start and stop conditions
Both DATA and CLOCK lines remain HIGH when the bus is not busy. As shown in Figure 5,
a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition
must be sent before each START condition.
7.6
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first. One data bit is transferred during each clock
Figure 4.
Data validity on the I2C Bus
Figure 5.
Timing diagram on I2C Bus



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