TDA7505 datasheet(31/38 Pages) STMICROELECTRONICS

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TDA7505

Functional description

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5.2.7

Debug interface

A multiplexed Debug Port is available for the DSP Cores. The debug logic is contained in the

core design of the DSP. The features of the Debug Port are listed below:

●

Breakpoint Logic

●

Trace Logic

●

Single stepping

●

Instruction Injection

●

Program Disassembly

5.2.8

General purpose input/output

The DSP requires a set of external general purpose input/output lines, and a reset line.

These signals are used by external devices to signal events to the DSP. The GPIO lines are

implemented as DSP 's peripherals. The GPIO lines are grouped in Port A, connected to

DSP 0, and Port B, connected to DSP1.

5.2.9

Asynchronous sample rate converter

The ASRC, embedded in the device, offers a fully digital stereo asynchronous sample rate

conversion of digital audio sources to the device's internal sample frequency. This solves the

problem of mixing audio sources with different sample rates.

The ASRC is able to do both up- and down-sampling. There is no need to explicitly program

the input and output sample rates, as the ASRC solves this problem with an automatic

Digital Ratio Locked Loop.

In case of down sampling, an internal low pass filter limits the bandwidth. Thus any down

folding products are avoided.

The ASRC is intended for applications up to 20 bit input word width. Digital Audio Sources

can be applied in general Serial Audio Interface format (3 wires) as well as in AES/EBU, IEC

958, S/PDIF and EIAJ CP-340 format (1 wire).

An interface to the DSP core offers the possibility of interrupt controlled sample delivery.

Furthermore, a programmable Control/Status Register inside the ASRC allows a great

variety of adjustments and status information.

The ASRC is intended for applications

–

up to 20 bit input and 24 bit output word width,

–

32kHz to 96kHz sample rate for input signal (SPDIF Receiver features)

–

32kHz to 48kHz sample rate for output signal.

5.2.10

SINCOS co-processor

The SINCOS is a cordic-based co-processor for calculation of sine and cosine without using

DSP resources.

5.2.11

PLL clock oscillator

The PLL Clock Oscillator can accept an external clock at CLKIN or it can be configured to

run with an internal oscillator when a crystal is connected across pins XTI & XTO. There is

an input divide block IDF (1 -> 32) at the XTI clock input and a multiply block MF (9 -> 128)

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