JS48F4400P0VB00 datasheet(52/99 Pages) NUMONYX

52 / 99 page

P30

Datasheet

November 2007

Order Number: 306666-11

10.3.3

WAIT Polarity

The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL) of

WAIT. When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is

asserted low. WAIT changes state on valid clock edges during active bus cycles (CE#

asserted, OE# asserted, RST# deasserted).

10.3.3.1

WAIT Signal Function

The WAIT signal indicates data valid when the device is operating in synchronous mode

(RCR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus.

When the device is operating in synchronous non-array read mode, such as read

status, read ID, or read query. The WAIT signal is also “deasserted” when data is valid

on the bus.

WAIT behavior during synchronous non-array reads at the end of word line works

correctly only on the first data access.

When the device is operating in asynchronous page mode, asynchronous single word

read mode, and all write operations, WAIT is set to a deasserted state as determined

by RCR[10]. See Figure 15, “Asynchronous Single-Word Read (ADV# Latch)” on

page 33, and Figure 16, “Asynchronous Page-Mode Read Timing” on page 34.

Figure 27: Example Latency Count Setting using Code 3

CLK

CE#

ADV#

A[MAX:0]

D[15:0]

Data

Code 3

Address

Data

R103

High-Z

Table 27: WAIT Functionality Table (Sheet 1 of 2)

Condition

WAIT

Notes

CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’

High-Z

CE# =’0’, OE# = ‘0’

Active

Synchronous Array Reads

Active

Synchronous Non-Array Reads

Active

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