CybraTech (2000) Ltd.
SOC-3000/i Scale-On-Chip
ASIC
Technical Specification
Revision B
Page 33
July, 2002
NOTE
When Control Register Address F101H, bit 7 is set to 1 (Released), key-code value bits 0
to 6 in address F101H are meaningless.
TABLE 15: KEYBOARD CONTROLLER DATA REGISTER BIT DEFINITIONS
BYTE # ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
1
F100H
X
X
X
X
X
X
X
Key Error
0 = Legal
1 = Error
2
F101H
Release Sign
0 = Pressed
1 = Released
D6
D5
D4
D3
D2
D1
D0
Operation
At power on, the keyboard controller is reset and the scanning rate is set to 10 µs.
Initialization:
To enable the keyboard controller:
1.
Enable the keyboard controller clock source in Clock Enable register C200H:
Set C200H, Bit 2 to 1.
2.
Reset the keyboard controller:
Write FF to register C400H.
3.
Set CFR address for keyboard controller function:
CFR addresses C10DH and C10EH = FF (Table 32, page 62).
This causes the following results:
•
Enables keyboard input pins (1 to 5 and 82 to 84) (Table 32; page 62; Table 1,
page 9; Table 2, page 12)
•
Enables keyboard output pins (74 to 81) (Table 32, Table 1, Table 2)
4.
Enable keyboard interrupt:
Set F100H, Bit 3 to 0.
5.
Set anti-bounce timeout:
Set F100H, Bits 0, 1 and 2, as shown in Table 14.
Normal Operation:
6.
Read keyboard key-code value bits, as follows:
•
Read register F100H, Bit 0:
If 0, key-code value is legal.
If 1, key-code value is illegal (Error).
•
Read key code from register F101H, bits 0 to 6:
When key pressed, values are valid.
•
Read F101H, bit 7:
If 0, key pressed and keyboard values (bits 0 to 6) are valid.
If 1, key released and keyboard values are meaningless.
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