AT91SAM7A2-AI datasheet(34/369 Pages) ATMEL

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PRELIMINARY

AT91SAM7A2

6021A–ATARM–07/04

The following figure shows a write cycle with two wait states.

Figure 22. Write Cycle with Two Wait States

Data Float Wait State

Data float wait states are added to avoid data bus conflict.

After a read access, the data float wait state gives more time for the external memory to

release the data bus.

After a write access the data float wait state gives more time for the EBI to release the

data bus.

The Data Float Output Time (t

DF) for each external memory device is programmed in the

TDF field of the AMC_CSR register for the corresponding chip select. The value (0-7

clock cycles) indicates the number of data float wait states to be inserted.

Data float wait state are asserted in between accesses.

Data float wait state insertion depends strongly on the previous access and the next

access contingent upon whether the state is a write or read cycle (early or standard) and

if it is on the same chip select.

The following table describes the data float wait state applied.

Address Valid

Address

NCS

NOE/NRD

Table 23. Data Float State Applied

Previous Access

Next Access

Number of Data Float Wait State Applied

Early Read Mode

Standard Read Mode

NCSx Read

NCSx Write

nTDF

NTDF

NCSx Write

NCSx Read

NCSx Write

NCSx Read

NCSy Read

Max(1, nTDFx)

NCSx Read

NCSy Write

Max(1, nTDFx)

NCSx Write

NCSy Read

NCSx Write

NCSy Write

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