AT91SAM7A2-AI datasheet(7/369 Pages) ATMEL

7 / 369 page

PRELIMINARY

AT91SAM7A2

6021A–ATARM–07/04

Product Overview

Enable/Disable/Status

Registers

In order to reduce code size and subsequently increase speed when accessing internal

peripherals, most of the registers have been split into three address locations:

•

The first address location (Enable or Set Register) is used to set a bit to a logical 1.

•

The second address location (Disable or Clear Register) is used to set a bit to a

logical 0.

•

The third address location (Status register or Mask Register) gives the current state

of the bit.

To set a bit to a logical 1 in the Status or Mask Register, a write command in the Enable

or Set Register must be performed with the corresponding bit at a logical 1.

To set a bit to a logical 0 in the Status or Mask Register, a write command in the Disable

or Clear Register must be performed with the corresponding bit at a logical 1.

Example

Supposing that the US0_PSR register value is 0x00000000. To enable the RXD and

SCK pins as PIOs in the USART0 block, 0x00050000 must be written in the US0_PER

Now if the software wants to disable the RXD pin as a PIO (i.e. enable it for USART0

use), a write access to the US0_PDR register with the value 0x00040000 must be per-

formed. The new value read in the US0_PSR register will be 0x00010000.

Key Access to Registers

Some bits in registers can be set to a value (0 or 1) only if the right key is written at the

same time.

Example

The TESTEN bit in the SFM_TM register can be set to a logical 0 or 1 only if the

KEY[15:0] bits are equal to 0xD64A.

To enable test mode, 0xD64A0002 must be written in the SFM_TM register.

To disable test mode, 0xD64A0000 must be written in the SFM_TM register.

Ghost Registers

The AT91SAM7A2 microcontroller integrates an ICE (In-Circuit Emulation) interface that

is associated with a JTAG connection and a software debugger that provides powerful

debug possibility.

Effectively,

•

A running program can be stopped.

•

Internal registers and internal/external memories can be monitored.

•

Instructions can be added when the core is stopped.

•

The program can be resumed.

However, some AT91SAM7A2 registers are "read-active", meaning that reading such

registers can affect the state of other registers. This is usual and wanted register behav-

ior. For example, in the ADC module, the bit EOC (End Of Conversion) is automatically

cleared when the DR (numerical value of the input converted) is read. The aim is to cut

off the amount of code needed in an application.

Meanwhile, when debugging software, users can monitor the value of a register, without

modifying the state of another register. For this purpose, for each module, a ghost regis-

AT91SAM7A2-AI bảng dữ liệu(PDF) 7 Page - ATMEL Corporation

AT91SAM7A2-AI bảng dữ liệu(HTML) 7 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL