AT89C51CC03U-RDTIM datasheet(84/183 Pages) ATMEL

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AT89C51CC03

4182B–CAN–09/03

Watchdog Timer During

Power-down Mode and

Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in

Power-down mode, the user does not need to service the WDT. There are 2 methods of

exiting Power-down mode: by a hardware reset or via a level activated external interrupt

which is enabled prior to entering Power-down mode. When Power-down is exited with

hardware reset, the Watchdog is disabled. Exiting Power-down with an interrupt is sig-

nificantly different. The interrupt shall be held low long enough for the oscillator to

stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the

WDT from resetting the device while the interrupt pin is held low, the WDT is not started

until the interrupt is pulled high. It is suggested that the WDT be reset during the inter-

rupt service for the interrupt used to exit Power-down.

To ensure that the WDT does not overflow within a few states of exiting powerdown, it is

best to reset the WDT just before entering powerdown.

In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting

AT89C51CC03 while in Idle mode, the user should always set up a timer that will period-

ically exit Idle, service the WDT, and re-enter Idle mode.

Table 44. WDTPRG Register

WDTPRG (S:A7h)

Watchdog Timer Duration Programming Register

Reset Value = XXXX X000b

765

43210

–––

––

Bit

Number

Bit

Mnemonic

Description

Reserved