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TMS320DM335 bảng dữ liệu(PDF) 96 Page - Texas Instruments

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tên linh kiện TMS320DM335
Giải thích chi tiết về linh kiện  Digital Media System-on-Chip (DMSoC)
PDF  156 Pages
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TMS320DM335 bảng dữ liệu(HTML) 96 Page - Texas Instruments

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5
DM335 Peripheral Information and Electrical Specifications
5.1
Parameter Information Device-Specific Information
TransmissionLine
4.0pF
1.85pF
Z0=50 Ω
(seenote)
Tester PinElectronics
Data SheetTimingReferencePoint
Output
Under
Test
42 Ω
3.5nH
DevicePin
(seenote)
5.1.1
Signal Transition Levels
Vref
Vref =VIL MAX(orVOL MAX)
Vref =VIH MIN(orVOH MIN)
5.1.2
Timing Parameters and Board Routing Analysis
TMS320DM335
Digital Media System-on-Chip (DMSoC)
SPRS528 – JULY 2008
www.ti.com
A.
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add
or
subtract
the
transmission
line
delay
(2
ns
or
longer)
from
the
data
sheet
timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
Figure 5-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,
Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V.
Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOLMAX and VOH MIN for output clocks.
Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels
The timing parameter values specified in this data sheet do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
DM335 Peripheral Information and Electrical Specifications
96
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