ST92F120JR9T datasheet(303/320 Pages) STMICROELECTRONICS

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ST92F120 - ELECTRICAL CHARACTERISTICS

WATCHDOG TIMING TABLE

(VDD =5V ± 10%, TA = –40°C to +105°C, CLoad = 50pF, fINTCLK = 24MHz, Push-pull output configuration,

unless otherwise specified)

Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,

watchdog prescaler and counter programmed values.

The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz, with minimum and

maximum prescaler value and minimum and maximum counter value.

Measurement points are VOH or VIH for positive pulses and VOL or VIL for negative pulses.

(1) Formula guaranteed by design.

Legend:

Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;

2 x OSCIN period when OSCIN is divided by 2;

OSCIN period x PLL factor when the PLL is enabled.

Psc = Watchdog Prescaler Register content (WD TPR): from 0 to 255

Cnt = Watchdog Couter Registers content (WDTRH,WD TRL): from 0 to 65535

TWDIN = Watchdog Input signal period (WDIN)

WATCHDOG TIMING

Symbol

Parameter

Value

Unit

Formula (1)

Min

Max

TwWDOL

WDOUT Low Pulse Width

4 x (Psc+1) x (Cnt+1) x Tck

167

2.8

(Psc+1) x (Cnt+1) x TWDIN

with TWDIN ≥ 8 x Tck

333

TwWDOH

WDOUT High Pulse Width

4 x (Psc+1) x (Cnt+1) x Tck

167

2.8

(Psc+1) x (Cnt+1) x TWDIN

with TWDIN ≥ 8 x Tck

333

TwWDIL

WDIN High Pulse Width

≥ 4 x Tck

167

TwWDIH

WDIN Low Pulse Width

≥ 4 x Tck

167

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