ST92141 datasheet(162/179 Pages) STMICROELECTRONICS

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ST92141 - ELECTRICAL CHARACTERISTICS

RCCU CHARACTERISTICS

(VDD = 5V ± 10%, TA = –40°C to +85°C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)

Note:

(1) Unless otherwise stated, typical data are based on TA=25°C and VDD=5V. They are only reported for design guidelines - not tested in pro-

duction.

(2) Data based on characterization results - not tested in production

RCCU TIMING TABLE

(VDD = 5V ± 10%, TA = –40°C to +85°C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)

Note:

(1) Depending on the delay between rising edge of RESET pin and the first rising edge of CLOCK1, the value can differ from the typical value

for +/- 1 CLOCK1 cycle.

Legend: Tosc = OSCIN period

PLL CHARACTERISTICS

(VDD = 5V ± 10%, TA = –40°C to +85°C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)

Note:

(1) Measured with PLL output clock frequency equal to 25MHz. Data based on characterization results - not tested in production.

Legend: Tosc = OSCIN period

Symbol

Parameter

Comment

Value (Note)

Unit

Min

Typ(1)

Max

VIHRS

RESET Input High Level

0.7VDD

VDD + 0.3

VILRS

RESET Input Low Level

– 0.3

0.3VDD

VHYRS

RESET Input Hysteresis(2)

900

ILKRS

RESET Pin Input Leakage

0V < VIN < VDD

– 10

+ 10

µA

Symbol

Parameter

Comment

Value (Note)

Unit

Min

Typ

Max

TFRS

RESET Input Filtered Pulse

TNFRS

RESET Input not Filtered

Pulse

µs

TRSPH

(1)

RESET Phase duration

20478 x Tosc

µs

TSTR

STOP Restart duration

DIV2 = 0

DIV2 = 1

10239 x Tosc

20478 x Tosc

µs

Symbol

Parameter

Comment

Value (Note)

Unit

Min

Typ

Max

FVCO

VCO Operating Frequency

MHz

TPLK

Lock-in Time

1000 x Tosc

µs

PLL Jitter

1.2 (1)

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