ST72C171 datasheet(23/152 Pages) STMICROELECTRONICS

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ST72C171

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4.4 CLOCK, RESET AND SUPPLY REGISTER DESCRIPTION

CLOCK

RESET

AND

SUPPLY

(CRSR)

Read /Write

Reset Value: 000x 000x (00h)

Bit 7:5 = Reserved.

Bit 4 = LVDRF

LVD Reset Flag

This bit indicates when set that the last Reset was

generated by the LVD block. It is set by hardware

(LVD reset) and cleared by software (writing zero)

or a Watchdog Reset. See WDGRF flag descrip-

tion for more details.

Bit 3 = Reserved.

Bit 2 = CSSIE

CSS Interrupt Enable

This bit allows to enable the interrupt when a dis-

trurbance is detected by the Clock Security Sys-

tem (CSSD bit set). It is set and cleared by soft-

ware.

0: Clock Filter interrupt disable

1: Clock Filter interrupt enable

Bit 1 = CSSD

CSS Safe Osc. Detection

This bit indicates that the safe oscillator of the CSS

block has been selected. It is set by hardware and

cleared by reading the CRSR register when the

original oscillator recovers.

0: Safe oscillator is not active

1: Safe oscillator has been activated

Bit 0 = WDGRF

WatchDog Reset Flag

This bit indicates when set that the last Reset was

generated by the Watchdog peripheral. It is set by

hardware (watchdog reset) and cleared by soft-

ware (writing zero) or an LVD Reset.

Combined with the LVDRF flag information, the

flag description is given by the following table.

Table 3. Supply, Reset and Clock Register Map and Reset Values

LVD

CSS

WDG

RESET Sources

LVDRF

WDGRF

External RESET pin

Watchdog

LVD

Address

(Hex.)

Label

7654

3210

0020h

MISCR

Reset Value

PEI3

PEI2

MCO

PEI1

PEI0

CP1

CP0

SMS

0025h

CRSR

Reset Value

LVDRF

CSSIE

CSSD

WDGRF

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