ST7285C datasheet(32/117 Pages) STMICROELECTRONICS

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ST7285C

SERIAL COMMUNICATIONS INTERFACE(Cont’d)

This TR factor is used only when the PSBRT fine

tuning factor is equal to 0; otherwise, TR is re-

placed by the PSBRT dividing factor.

Bit-2 = SCR2

Receiver rate divisor MSB

Bit-1 = SCR1

Receiver rate divisor NSB

Bit-0 = SCR0

Receiver rate divisor LSB

These 3 bits, in conjunction with the 2 previous bits

define the total division applied to the bus clock to

yield the receive rate clock in conventional Baud

Rate Generator mode..

This RR factor is used only when the PSBRR fine

tuning factor is equal to 0; otherwise, RR is re-

placed by the PSBRR dividing factor.

4.2.7.6 External Receive Prescaler Division

Address: 0055h

—

Read/Write

Reset Value: 00h

Allows setting of the External Prescaler rate divi-

sion factor for the receive circuit.

When the register is set to 00h, the conventional

Baud Rate Generator is used for the receive cir-

cuit, otherwise the master clock frequency is divid-

ed by the binary factor set in the PSCBRR register

(in the range 1 to 255).

4.2.7.7 External Transmit Prescaler Division

Address: 0057h

—

Read/Write

Reset Value: 00h

Allows setting of the External Prescaler rate divi-

sion factor for the transmit circuit.

When the register is set to 00h, the conventional

Baud Rate Generator is used for the transmit cir-

cuit, otherwise the master clock frequency is divid-

ed by the binary factor set in the PSCBRTregister

(in the range 1 to 255).

SCT2

SCT1

SCT0

TR dividing factor

128

SCR2

SCR1

SCR0

RR dividing factor

128

4321

PRBR

4321

PTBR

PTB R

PTBR

PTB R

PTBR

PTB R

PTBR

PTB R

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