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ST7285C bảng dữ liệu(PDF) 90 Page - STMicroelectronics

tên linh kiện ST7285C
Giải thích chi tiết về linh kiện  8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
PDF  117 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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ST7285C bảng dữ liệu(HTML) 90 Page - STMicroelectronics

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ST7285C
CONTROL TIMING (Cont’d)
SERIAL PERIPHERAL INTERFACE
Symbol
Ref.
Characteristics
f
OSC = 8.0MHz
Unit
Min.
Max.
Operating Frequency =fOSC/2 =fOP
fOP(m)
Master
dc
0.5
fOP
fOP(s)
Slave
dc
4.0
MHz
1
Cycle Time
tCYC(m)
Master
2.0
tCYC
tCYC(s)
Slave
240
ns
2
Enable Lead Time
ns
tlead(m)
Master
(1)
tlead(s)
Slave
120
3
Enable Lag time
ns
Master
(1)
Slave
120
4
Clock (SCK)High Time
tW(SCKH)
Master
100
ns
tW(SCKH)
Slave
90
ns
5
Clock (SCK) Low Time
tW(SCKL)
Master
100
ns
tW(SCKL)
Slave
90
ns
6
Data Set-up Time
tSU(m)
Master
100
ns
tSU(s)
Slave
100
ns
7
Data Hold Time (Inputs)
tH(m)
Master
100
ns
tH(s)
Slave
100
ns
tA
8
Access Time (Time to Data Active from High Impedance State)
ns
Slave
0
120
tDIS
9
Disable Time (Hold Time to High Impedance State)
ns
Slave
240
10
Data Valid
tV(m)
Master (Before Capture Edge)
0.25
tCYC(m)
tV(s)
Slave (After Enable Edge) (2)
120
ns
11
Data Hold Time (Outputs)
tHO(m)
Master (Before Capture Edge)
0.25
tCYC(m)
tHO(s)
Slave (After Enable Edge)
0
ns
12
Rise Time (20% VDD to 70% VDD,CL = 200pF)
tRM
SPI Outputs (SCK, MOSI, MISO)
100
ns
tRS
SPI Inputs (SCK, MOSI, MISO, SS)
2.0
µs
13
Fall Time (70% VDD to 20% VDD,CL
tFM
SPI Outputs (SCK, MOSI, MISO)
100
ns
tFS
SPI Inputs (SCK, MOSI, MISO, SS)
2.0
µs



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