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ST62T53C bảng dữ liệu(PDF) 22 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI
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ST62T53C/T60C/T63C ST62E60C
CLOCK SYSTEM (Cont’d)
Figure 12. Clock Circuit Block Diagram
Figure 13. Maximum Operating Frequency (fMAX) versus Supply Voltage (VDD)
Notes:
1. In this area, operation is guaranteed at the
quartz crystal frequency.
2. When the OSG is disabled, operation in this
area is guaranteed at the crystal frequency. When
the OSG is enabled, operation in this area is guar-
anteed at a frequency of at least fOSG Min.
3. When the OSG is disabled, operation in this
area is guaranteed at the quartz crystal frequency.
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept a fOSG.
4. When the OSG is disabled, operation in this
area is not guaranteed
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept at fOSG.
MAIN
OSCILLATOR
OSG
LFAO
M
U
X
Core
:13
:12
:1
TIMER 1
Watchdog
POR
fINT
Main Oscillator off
OSCILLATOR
DIVI DER
RS0,RS1
1
2.5
3.6
4
4.5
5
5.5
6
8
7
6
5
4
3
2
Maximum FREQU ENCY (MHz)
SUPPLY VOLTAGE (VDD)
3
4
3
2
1
fOSG
fOSG Min (at 85°C)
VR01807J
fOSG Min (at 125°C)
22



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