ST62T53C datasheet(14/86 Pages) STMICROELECTRONICS

14 / 86 page

14/86

ST62T53C/T60C/T63C ST62E60C

1.4 PROGRAMMING MODES

1.4.1 Option Bytes

The two Option Bytes allow configuration capabili-

ty to the MCUs. Option byte’s content is automati-

cally read, and the selected options enabled, when

the chip reset is activated.

It can only be accessed during the programming

mode. This access is made either automatically

(copy from a master device) or by selecting the

OPTION BYTE PROGRAMMING mode of the pro-

grammer.

The option bytes are located in a non-user map.

No address has to be specified.

EPROM Code Option Byte (LSB)

EPROM Code Option Byte (MSB)

D15-D13. Reserved. Must be cleared.

ADC SYNCHRO

. When set, an A/D conversion is

started upon WAIT instruction execution, in order

to reduce supply noise. When this bit is low, an A/

D conversion is started as soon as the STA bit of

the A/D Converter Control Register is set.

D11. Reserved

, must be set to one.

D10. Reserved

, must be cleared.

NMI PULL.

NMI Pull-Up. This bit must be set high

to configure the NMI pin with a pull-up resistor.

When it is low, no pull-up is provided.

LVD.

LVD RESET enable.When this bit is set, safe

RESET is performed by MCU when the supply

voltage is too low. When this bit is cleared, only

power-on reset or external RESET are active.

PROTECT.

Readout Protection. This bit allows the

protection of the software contents against piracy.

When the bit PROTECT is set high, readout of the

OTP contents is prevented by hardware.. When

this bit is low, the user program can be read.

EXTCNTL.

External STOP MODE control.. When

EXTCNTL is high, STOP mode is available with

watchdog active by setting NMI pin to one. When

EXTCNTL is low, STOP mode is not available with

the watchdog active.

PB2-3 PULL. When set this bit removes pull-up at

reset on PB2-PB3 pins. When cleared PB2-PB3

pins have an internal pull-up resistor at reset.

PB0-1 PULL. When set this bit removes pull-up at

reset on PB0-PB1 pins. When cleared PB0-PB1

pins have an internal pull-up resistor at reset.

WDACT. This bit controls the watchdog activation.

When it is high, hardware activation is selected.

The software activation is selected when WDACT

is low.

DELAY. This bit enables the selection of the delay

internally generated after the internal reset (exter-

nal pin, LVD, or watchdog activated) is released.

When DELAY is low, the delay is 2048 cycles of

the oscillator, it is of 32768 cycles when DELAY is

high.

OSCIL.

Oscillator selection. When this bit is low,

the oscillator must be controlled by a quartz crys-

tal, a ceramic resonator or an external frequency.

When it is high, the oscillator must be controlled by

an RC network, with only the resistor having to be

externally provided.

OSGEN.

Oscillator Safe Guard. This bit must be

set high to enable the Oscillator Safe Guard.

When this bit is low, the OSG is disabled.

The Option byte is written during programming ei-

ther by using the PC menu (PC driven Mode) or

automatically (stand-alone mode).

PRO-

TECT

EXTC-

NTL

PB2-3

PULL

PB0-1

PULL

WDACT

DE-

LAY

OSCIL

OSGEN

ADC

SYNCHRO

NMI

PULL

LVD

ST62T53C bảng dữ liệu(PDF) 14 Page - STMicroelectronics

ST62T53C bảng dữ liệu(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

bảng dữ liệu tải về

Link URL