ST40RA datasheet(15/94 Pages) STMICROELECTRONICS

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5 System configuration

ST40RA

15/94

STMicroelectronics

ADCS 7260755H

5.3

Interrupt mapping

For full details on the interrupt controller see

ST40 System Architecture Manual Volume 1:System.

The mapping of the CPU interrupts is described in

Section 5.3.1, Section 5.3.2 and Section 5.3.3.

Note:

Some INTEVT codes are shown as reserved in Table 3 and therefore cannot be generated by this

device.

5.3.1

ST40 core interrupt allocation

The allocation of core interrupts is as shown in

Table 3.

Interrupt source

INTEVT

code

Interrupt priority

IPR

bit numbers

Priority

within IPR

setting unit

Value

Initial value

NMI

0x1C0

IRL

level

encoding

IRL3–IRL0 = F

0x200

IRL3–IRL0

= E

0x220

IRL3–IRL0

= D

0x240

IRL3–IRL0

= C

0x260

IRL3–IRL0

= B

0x280

IRL3–IRL0

= A0x2A0

IRL3–IRL0

= 90x2C0

IRL3–IRL0

= 80x2E0

IRL3–IRL0

= 7

0x300

IRL3–IRL0

= 6

0x320

IRL3–IRL0

= 5

0x340

IRL3–IRL0

= 4

0x360

IRL3–IRL0

= 3

0x380

IRL3–IRL0

= 20x3A0

IRL3–IRL0

= 10x3C0

IRL

independent

encoding

IRL0

0x240

15 to 0

IPRD[15:12]

IRL1

0x2A0

15 to 0

IPRD[11:8]

IRL2

0x300

15 to 0

IPRD[7:4]

IRL3

0x360

15 to 0

IPRD[3:0]

H-UDI

0x600

15 to 0

IPRC[3:0]

TMU0

TUNI0

0x400

15 to 0

IPRA[15:12]

TMU1

TUNI1

0x420

0 to 15

IPRA[11:8]

TMU2

TUNI2

0x440

0 to 15

IPRA[7:4]

High

TICPI2

0x460

Low

Table 3: ST40 core interrupt allocation (page 1 of 2)

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