ST10R272LT1 datasheet(67/77 Pages) STMICROELECTRONICS

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ST10R272L - ELECTRICAL CHARACTERISTICS

Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

The leading edge of the respective command depends on RW-delay.

3READY (or READY) sampled HIGH (resp. LOW) at this sampling point generates a

READY controlled waitstate, READY (resp. READY) sampled LOW (resp. HIGH) at this

sampling point terminates the currently running bus cycle.

4READY (resp. READY) may be deactivated in response to the trailing (rising) edge of the

corresponding command (RD or WR).

If the Asynchronous READY (or READY) signal does not fulfill the indicated setup and

hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t

37 in order to be safely synchronized. This is guaranteed, if READY is removed in

response to the command (see Note 4)).

Figure 24 CLKOUT and READY/READY

Sync

READY

t35

t36

t35

t36

Async

READY

t58

t59

t58

t59

t37

t60

see 6)

CLKOUT

ALE

t30

t34

Sync

READY

t35

t36

t35

t36

Async

READY

t58

t59

t58

t59

waitstate

READY

MUX/Tristate 6)

t32

t33

t29

Running cycle 1)

t31

t37

Command

RD, WR

t60

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