ST10F280 datasheet(127/186 Pages) STMICROELECTRONICS

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ST10F280

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16 - WATCHDOG TIMER

The Watchdog Timer is a fail-safe mechanism

which prevents the microcontroller from malfunc-

tioning for long periods of time.

The Watchdog Timer is always enabled after a

reset of the chip and can only be disabled in the

time interval until the EINIT (end of initialization)

instruction has been executed.

Therefore, the chip start-up procedure is always

monitored. The software must be designed to ser-

vice the watchdog timer before it overflows. If, due

to hardware or software related failures, the soft-

ware fails to do so, the watchdog timer overflows

and generates an internal hardware reset. It pulls

the RSTOUT pin low in order to allow external

hardware components to be reset.

Each of the different reset sources is indicated in

the WDTCON register.

The indicated bit are cleared with the EINIT

instruction. The origine of the reset can be identi-

fied during the initialization phase.

WDTCON (FFAEh / D7h)

SFR

Reset Value: 00xxh

Notes: 1. More than one reset indication flag may be set. After EINIT, all flags are cleared.

2. Power-on is detected when a rising edge from Vcc = 0 V to Vcc > 2.0 V is recognized.

765

4321

WDTREL

PONR LHWR SHWR

SWR

WDTR WDTIN

RRRR

WDTIN

Watchdog Timer Input Frequency Selection

‘0’: Input Frequency is fCPU/2.

‘1’: Input Frequency is fCPU/128.

WDTR1

Watchdog Timer Reset Indication Flag

Set by the watchdog timer on an overflow.

Cleared by a hardware reset or by the SRVWDT instruction.

SWR1

Software Reset Indication Flag

Set by the SRST execution.

Cleared by the EINIT instruction.

SHWR1

Short Hardware Reset Indication Flag

Set by the input RSTIN.

Cleared by the EINIT instruction.

LHWR1

Long Hardware Reset Indication Flag

Set by the input RSTIN.

Cleared by the EINIT instruction.

PONR1- 2

Power-On (Asynchronous) Reset Indication Flag

Set by the input RSTIN if a power-on condition has been detected.

Cleared by the EINIT instruction.

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