ST10 datasheet(60/65 Pages) STMICROELECTRONICS

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ST10C167

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XX.4.12 - External bus arbitration

VDD =5V ± 10%, VSS = 0V, TA = -40 to +125°C

CL (for Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100pF

CL (for Port 6, CS) = 100pF

Note

1. Guaranteed by design characterization.

Notes 1. The ST10C167 will complete the currently running bus cycle before granting bus access.

2. This is the first possibility for BREQ to become active.

3. The CS outputs will be resistive high (pullup) after

64.

Table 21 : External bus arbitration

Symbol

Parameter

Max. CPU Clock

= 25MHz

Variable CPU Clock

1/2TCL = 1 to 25MHz

Unit

Min.

Max.

Min.

Max.

t61

HOLD input setup time to CLKOUT

–

t62

CLKOUT to HLDA hig or BREQ low delay

–

t63

CLKOUT to HLDA low or BREQ high delay

–

t64

CSx release

–1

–

t65

CSx drive

-4

t66

Other signals release

–1

–

t67

Other signals drive

-4

Figure 23 : External bus arbitration, releasing the bus

CLKOUT

HOLD

t61

HLDA

t63

Other

Signals

t66

CSx

(On P6.x)

t64

BREQ

t62

XX - ELECTRICAL CHARACTERISTICS (continued)

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