ST10F167 datasheet(50/69 Pages) STMICROELECTRONICS

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ST10F167

20.5.5 External Clock Drive XTAL1

VDD =5 V ± 5%, VSS =0 V, TA = -40 to +85 °C

1) Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal.

Figure 20.6

External Clock Drive XTAL1

20.5.6 Memory Cycle Variables

The timing tables below use three variables which

are derived from the BUSCONx registers and rep-

resent the special characteristics of the pro-

grammed memory cycle. The following table de-

scribes, how these variables are to be computed.

Table 20.4

External Clock Drive Characteristics

Parameter

Symbol

Direct Drive 1:1

PLL 1:4

Unit

min.

max.

min.

max.

Oscillator period

OSC

50 1)

1000

200

333

High time

–

Low time

–

Rise time

–

Fall time

–

VIL

tOSC

VIH2

Table 20.5

Memory Cycle Variable Definition

Description

Symbol

Values

ALE Extension

TCL * <ALECTL>

Memory Cycle Time Waitstates

2TCL * (15 - <MCTC>)

Memory Tristate Time

2TCL * (1 - <MTTC>)

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