ST10F167 datasheet(19/69 Pages) STMICROELECTRONICS

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ST10F167

CENTRAL PROCESSING UNIT (CPU)

Figure 7.1

CPU Block Diagram

The main core of the CPU consists of a 4-stage in-

struction pipeline, a 16-bit arithmetic and logic unit

(ALU) and dedicated SFRs. has been added for a

separate multiply and divide unit, a bit-mask gen-

erator and a barrel shifter.

Based on these hardware provisions, most of the

ST10F167’s instructions can be executed in one

machine cycle. This requires 100ns at 20MHz

CPU clock. For example, shift and rotate instruc-

tions are always processed during one machine

cycle independent of the number of bits to be shift-

ed. All multiple-cycle instructions have been opti-

mized for speed: branches in 2 cycles, a 16

× 16

bit multiplication in 5 cycles and a 32-/16 bit divi-

sion in 10 cycles. The ‘Jump Cache’ pipeline opti-

mization, reduces the execution time of repeatedly

performed jumps in a loop, from 2 cycles to 1 cy-

cle.

The CPU includes an actual register context. This

consists of up to 16 wordwide GPRs which are

physically allocated within the on-chip RAM area.

A Context Pointer (CP) register determines the

base address of the active register bank to be ac-

cessed by the CPU at a time. The number of reg-

ister banks is only restricted by the available inter-

nal RAM space. For easy parameter passing, a

A system stack of up to 2048 bytes is provided as

a storage for temporary data. The system stack is

allocated in the on-chip RAM area, and it is ac-

cessed by the CPU via the stack pointer (SP) reg-

ister. Two separate SFRs, STKOV and STKUN,

are implicitly compared against the stack pointer

value upon each stack access for the detection of

a stack overflow or underflow.

FLASH

Internal

RAM

2KByte

R15

General

Purpose

Registers

R15

MDH

MLD

Barrel-Shift

Mul./Div.-HW

Bit-Mask Gen.

ALU

16-Bit

Context Ptr

STKOV

STKUN

Exec. Unit

Instr. Ptr

Instr. Reg

4-Stage

Pipeline

PSW

SYSCON

BUSCON 0

BUSCON 1

BUSCON 2

BUSCON 3

BUSCON 4

ADDRSE L 1

ADDRSE L 2

ADDRSE L 3

ADDRSE L 4

Data Pg. Ptrs

Code Seg. Ptr.

CPU

ROM

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