NRF52811-QCAA-R datasheet(351/444 Pages) NORDIC

351 / 444 page

Peripherals

ADDR

Stretch

ADDR

Figure 134: A double repeated start sequence using the

SUSPEND task to secure safe operation in low priority interrupts

6.25.5 Low power

When putting the system in low power and the peripheral is not needed, lowest possible power

consumption is achieved by stopping, and then disabling the peripheral.

The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent,

software shall wait until the STOPPED event was received as a response before disabling the peripheral

through the ENABLE register.

6.25.6 Master mode pin configuration

The SCL and SDA signals associated with the TWI master are mapped to physical pins according to the

configuration specified in the PSEL.SCL and PSEL.SDA registers respectively.

The PSEL.SCL and PSEL.SDA registers and their configurations are only used as long as the TWI master is

enabled, and retained only as long as the device is in ON mode. When the peripheral is disabled, the pins

will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n]

To secure correct signal levels on the pins used by the TWI master when the system is in OFF mode, and

when the TWI master is disabled, these pins must be configured in the GPIO peripheral as described in

GPIO configuration before enabling peripheral on page 351.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in

unpredictable behavior.

TWI master signal

TWI master pin

Direction

Output value

Drive strength

SCL

As specified in PSEL.SCL

Input

Not applicable

S0D1

SDA

As specified in PSEL.SDA

Input

Not applicable

S0D1

Table 104: GPIO configuration before enabling peripheral

6.25.7 Registers

Base address

Peripheral

Instance

Description

Configuration

0x40003000

TWIM

TWIM0

Two-wire interface master

Table 105: Instances

4454_140 v1.0

351

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