NRF52811-QCAA-R datasheet(292/444 Pages) NORDIC

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Peripherals

If the ENDTX event has not already been generated when the SPI master has come to a stop, the SPI

master will generate the ENDTX event explicitly even though all bytes in the TXD buffer, as specified in the

TXD.MAXCNT register, have not been transmitted.

The SPI master is a synchronous interface, and for every byte that is sent, a different byte will be received

at the same time; this is illustrated in SPI master transaction on page 292.

START

CPU

ENDTX

ORC

CSN

SCK

MOSI

m-2

m-1

MISO

ENDRX

Figure 116: SPI master transaction

6.19.2 Master mode pin configuration

The SCK, MOSI, and MISO signals associated with the SPI master are mapped to physical pins according to

the configuration specified in the PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers respectively.

The PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and their configurations are only used as long as the

SPI master is enabled, and retained only as long as the device is in ON mode. PSEL.SCK, PSEL.MOSI and

PSEL.MISO must only be configured when the SPI master is disabled.

To secure correct behavior in the SPI, the pins used by the SPI must be configured in the GPIO peripheral

as described in GPIO configuration on page 292 prior to enabling the SPI. This configuration must be

retained in the GPIO for the selected IOs as long as the SPI is enabled.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in

unpredictable behavior.

SPI master signal

SPI master pin

Direction

Output value

SCK

As specified in PSEL.SCK

Output

Same as CONFIG.CPOL

MOSI

As specified in PSEL.MOSI

Output

MISO

As specified in PSEL.MISO

Input

Not applicable

Table 86: GPIO configuration

4454_140 v1.0

292

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