NRF52811-QCAA-R datasheet(253/444 Pages) NORDIC

253 / 444 page

Peripherals

Sending a TRIGOVRFLW task sets the COUNTER to a value close to overflow. However, since the update

of COUNTER relies on a stable LFCLK, sending this task while LFCLK is not running will start LFCLK,

but the update will then be delayed by the same amount of time of up to ~250 us. The figures show

the smallest and largest delays to on the START task which appears as a +/-15 μs jitter on the first

COUNTER increment.

0x000

SysClk

LFClk

PRESC

COUNTER

X+1

First tick

START

>= ~15 us

X+2

X+3

0 or more SysClk before

Figure 101: Timing diagram - JITTER_START-

0x000

SysClk

LFClk

PRESC

COUNTER

First tick

START

<= ~250 us

X+1

X+2

Figure 102: Timing diagram - JITTER_START+

6.16.9 Reading the COUNTER register

To read the COUNTER register, the internal <<COUNTER>> value is sampled.

To ensure that the <<COUNTER>> is safely sampled (considering an LFCLK transition may occur during a

read), the CPU and core memory bus are halted for three cycles by lowering the core PREADY signal. The

Read takes the CPU 2 cycles in addition resulting in the COUNTER register read taking a fixed five PCLK16M

clock cycles.

SysClk

LFClk

<<COUNTER>>

N-1

PREADY

COUNTER_READ

COUNTER

375.2 ns

Figure 103: Timing diagram - COUNTER_READ

4454_140 v1.0

253

NRF52811-QCAA-R bảng dữ liệu(PDF) 253 Page - Nordic Semiconductor

NRF52811-QCAA-R bảng dữ liệu(HTML) 253 Page - Nordic Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL