NRF52811-QCAA-R datasheet(139/444 Pages) NORDIC

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Peripherals

tPDM,CLK

CLK

tPDM,s

DIN(R)

DIN (L)

tPDM,h=tPDM,ci

tPDM,s tPDM,h=tPDM,ci

tPDM,cv

Figure 45: PDM timing diagram

6.11 PPI — Programmable peripheral interconnect

The programmable peripheral interconnect (PPI) enables peripherals to interact autonomously with each

other using tasks and events independent of the CPU. The PPI allows precise synchronization between

peripherals when real-time application constraints exist and eliminates the need for CPU activity to

implement behavior which can be predefined using PPI.

Peripheral 1

Peripheral 2

Peripheral 1

Peripheral 2

Event 1

Event 2

Event 1

Event 2

Event 3

Task 1

Task 2

Task 3

Task 1

CH[0].EEP

CH[1].EEP

CH[n].EEP

CH[0].TEP

CHEN

16MHz

FORK[0].TEP

CHG[0]

CHG[m]

...

Figure 46: PPI block diagram

The PPI system has, in addition to the fully programmable peripheral interconnections, a set of channels

where the event end point (EEP) and task end points (TEP) are fixed in hardware. These fixed channels can

be individually enabled, disabled, or added to PPI channel groups (see CHG[n] registers), in the same way

as ordinary PPI channels.

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