PSD511B1 datasheet(126/153 Pages) STMICROELECTRONICS

126 / 153 page

PSD5XX Family

123

-20

-25

EPROM_CMiser

Symbol

Parameter

Conditions

Min Max Min Max

Unit

tLVLX

ALE or AS Pulse Width

tAVLX

Address Setup Time

(Note 4)

tLXAX

Address Hold Time

(Note 4)

tAVQV

Address Valid to Data Valid

(Note 4)

200

250

Add 20

t SLQV

CS Valid to Data Valid

200

275

Add 20

RD to Data Valid 8/16-Bit Bus

(Note 1)

RD to Data Valid 8-Bit Bus,

t RLQV

8031 Separate Mode

(Note 2)

RD to Data Valid from Interrupt Controller (Note 3)

t RHQX

RD Data Hold Time

(Note 1)

tRLRH

RD Pulse Width

(Note 1)

tRHQZ

RD to Data High-Z

(Note 1)

tEHEL

E Pulse Width

tTHEH

R/W Setup Time to Enable

tELTL

R/W Hold Time After Enable

In 16-Bit Data Bus

tAVPV

Address Input Valid to

Mode (Note 5)

Address Output Delay

In 8-Bit Data Bus

Mode (Note 5)

Read Timing (3.0 V ± 10%)

Explanation of AC Symbols for Non ZPLD Timing.

Example:

t AVLX Time from Address Valid to ALE Invalid.

A – Address

L – Logic Level Low or ALE

T – R/W

C – Power Down

N – Reset

t – Time

D– Input Data

P – Port Signal

V – Valid

E –E

Q – Output Data

X – No Longer a Valid Logic Level

H – Logic Level High

R – WR, UDS, LDS, DS, IORD, PSEN

Z – Float

I – Interrupt

S – Chip Select

13.11 Microcontroller Interface –AC/DC Parameters

(ZPSD5XXV Versions)

NOTES: 1. RD timing has the same timing as PSEN, DS, LDS, UDS signals (in 8031 combined mode).

2. RD and PSEN have the same timing for 8031 separate mode.

3. Read to Data Valid of the Interrupt Request Latch and Interrupt Priority Status. RD timing has the same timing as PSEN, DS, LDS,

UDS signals.

4. Any input used to select an internal ZPSD5XX function.

5. In multiplexed mode latched address generated from ADIO delay to address output on any Port.

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