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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PSD511B1 bảng dữ liệu(PDF) 122 Page - STMicroelectronics |
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PSD511B1 bảng dữ liệu(HTML) 122 Page - STMicroelectronics |
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122 / 153 page  PSD5XX Family 119 -70 -90** -15 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max Min Max OFF * Unit fMAX Maximum Frequency 36.00 30.00 22.00 0 MHz tCHCL Clock High Time 10 12 15 0 ns tCLCH Clock Low Time 10 12 15 0 ns tCHPV Clock to Output Delay 28 30 33 0 ns tCHPV1 Clock to Watchdog Output Dealy 50 50 58 Add 10 ns tLVCH Input Setup Time Relative to Rising Pin Input 15 17 20 Add 10 Clock Edge (Note 2) ns tLVCH1 Input Setup Time PLD Relative to Rising Combinatorial 25 27 31 (Note 2) ns Clock Edge Input tMIN Minimum Clock Period 1/fMAX 28 33 45 0 ns Counter/Timer Timing (5 V ± 10%) AC/DC Parameters – ZPLD Timing Parameters (5 V ± 10% Versions) -70 -90** -15 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max Min Max OFF * Unit tIVIV Interrupt Request Input to Interrupt Output (Note 3) 40 50 65 0 ns tRXIX Read Vector to Interrupt Request Clear 30 40 55 0 ns tILIL Interrupt Request Minimum Pulse Width 18 20 35 0 ns tRLQV RD to Data Valid Interrupt Controller (Note 1) 32 38 45 0 ns Interrupt Timing (5 V ± 10%) NOTES: 1. Read to Data Valid of the Interrupt Request Latch and Interrupt Priority Status. RD timing has the same timing as PSEN, DS, LDS, UDS signals. 2. For inputs which use PPLD only. 3. This timing is only valid when read to the interrupt request latch and priority status latch are not valid. **If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 10 ns to the timing parameters. **The -90 speed is available only on Industrial Temperature Range product. |
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