ADATE320 datasheet(20/78 Pages) AD

20 / 78 page

Data Sheet

ADATE320

SPECIFICATIONS

analog.com

Rev. C | 20 of 78

Table 13.

Parameter

Min

Typ

Max

Unit

Test Level

Test Conditions/Comments

Input Bias Current

−10

+10

µA

Tested at 0.0 V and VDD; RST tested at VDD; RST has an internal 50 kΩ

pull-up to VDD

SCLK Crosstalk on DUTx Pin

DCL disabled, PPMU forcing 0.0 V

Serial Output

Logic High

VDD − 0.5

VDD

SDO, sourcing 2 mA

Logic Low

0.0

0.5

Sinking 2 mA

BUSY Output Characteristics

Open-drain output

Off State Leakage

500

BUSY pin not asserted, apply VDD to pin and measure leakage current

Maximum On Voltage at 2 mA

0.01

0.7

BUSY pin asserted, force 2 mA into pin and measure voltage

SPI TIMING SPECIFICATIONS

Table 14.

Parameter

Symbol

Min

Typ

Max

Unit

Test Level

Description

SCLK Operating Frequency

fCLK

MHz

0.5

100

MHz

SCLK High Time

tCH

4.5

SCLK Low Time

tCL

4.5

CS to SCLK Setup at Assert

tCSAS

1.5

Setup time of CS assert to next rising edge of SCLK.

CS to SCLK Hold at Assert

tCSAH

1.5

Hold time of CS assert to next rising edge of SCLK.

CS to SCLK Setup at Release

tCSRS

1.5

Setup time of CS release to next rising edge of SCLK.

CS to SCLK Hold at Release

tCSRH

1.5

Hold time of CS release to next rising edge of SCLK.

This parameter is only critical if the number of SCLK

cycles from previous release of CS is the minimum

specified by the tCSAM parameter.

CS Assert to SDO Active

tCSO

Delay time from CS assert to SDO active state.

CS Release to SDO High-Z

tCSZ

Delay from CS release to SDO high-Z state, strongly

influenced by external SDO pin loading.

CS Release to Next Assert

tCSAM

Cycles

Minimum release time of CS between consecutive

assertions of CS. This parameter is specified in units of

SCLK cycles, more specifically in terms of rising edges

of the SCLK input.

SDI to SCLK Setup

tDS

Setup time of SDI data prior to next rising edge of

SCLK.

SDI to SCLK Hold

tDH

Hold time of SDI data following previous rising edge of

SCLK.

SCLK to Valid SDO

tDO

Propagation delay from rising edge of SCLK to valid

SDO data.

BUSY Assert from CS/RST

tBUSA

Propagation delay from first rising SCLK following valid

CS release (or RST release in the case of hardware

reset) to BUSY assert.

BUSY Width

tBUSW

Following CS

Cycles

Delay time from first rising SCLK after valid CS release

to BUSY release. Satisfies the requirements detailed in

the SPI Clock Cycles and the BUSY Pin section, except

following RST or software reset.

Following RST

744

Cycles

Delay time from first rising SCLK after RST release (or

valid CS release in the case of software reset) to BUSY

release. Satisfies the requirement of synchronous reset

sequence detailed in the SPI Clock Cycles and the

BUSY Pin section.

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