ADATE320 datasheet(54/78 Pages) AD

54 / 78 page

Data Sheet

ADATE320

THEORY OF OPERATION

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Rev. C | 54 of 78

Table 26. PPMU Transfer Functions

PPMU Mode

Transfer Functions1

Uncalibrated PPMU DAC Settings to Achieve Specified PPMU Range

VDUTx = PPMUx

−1.5 V < PPMUx < +4.5 V

IDUTx = (PPMUx − (VREF − VREFGND))/(5 × RPPMU)

0.0 V < PPMUx < 5.0 V

VPPMU_Mx = VDUTx (internal sense path)

Not applicable

VPPMU_Mx = VPPMU_Sx (external sense path)

Not applicable

VPPMU_Mx = (VREF − VREFGND) + (5 × IDUTx × RPPMU) + VDUTGND

Not applicable

1 RPPMU = 12.5 Ω for Range A, 500 Ω for Range B, 5.0 kΩ for Range C, 50 kΩ for Range D, and 250 kΩ for Range E.

Table 27. Temperature Sensor Transfer Function

Temperature

Output

0 K

0.00 V

300 K

3.00 V

TKELVIN

0.00 V + (TKELVIN ) × 10 mV/K

DAC Gain and Offset Correction

Each analog function within the ADATE320 has independent gain

(m) and offset (c) calibration registers that allow digital trim of

first-order errors in the analog signal chain. These registers correct

errors in the pin electronics transfer functions as well as errors

intrinsic to the DAC itself.

The m and c registers are volatile and must be reloaded after each

power-on cycle as part of a calibration routine if values other than

the defaults are required. The registers are not cleared by any reset

operation (although the DAC_CAL_ENABLE bit is cleared following

reset).

The gain and offset calibration function can be bypassed by clear-

ing the DAC_CAL_ENABLE bit in the DAC control register (see

Figure 145). This bypass mode is available only on a per chip

basis. In other words, it is not possible to bypass the calibration

function for a specific subset of the DACs.

The calibration function, when enabled, adjusts the numerical data

sent to each DAC according to the following equation:

X2= m+1216 ×X1 + c−215

(1)

where:

X2 is the 16-bit data-word gated into the physical DAC, and re-

turned by subsequent SPI read from that same DAC.

m is the code in the respective DAC gain calibration register (the

default code is 0xFFFF = 216 − 1).

X1 is the 16-bit data-word written by the user to the DAC via the

SPI.

c is the code in the respective DAC offset calibration register (the

default code is 0x8000 = 215).

From Equation 1, it can be seen that the gain applied to any written

X1 data is always ≤1.0, with the effect that the effective output of

a DAC can only be made smaller in magnitude by the calibration

mechanism. To compensate for this imposed limitation, each of the

analog signal paths in the pin electronics functions are guaranteed

by designed to have a gain ≥1.0 when the default m register values

are applied. A signal path gain ≥1.0 guarantees that proper gain

calibration can always be achieved by multiplying down.

DAC X2 Registers and SPI Readback

When data is written via the SPI to a particular DAC, that data is

operated on in accordance with Equation 1. The results are stored

in an X2 register associated with that DAC (see Figure 130).

There is only a single physical X2 register per DAC, and it is the

value of this X2 register that is eventually gated into the physical

DAC at the time of analog update, which can be either in immediate

or deferred mode. It is also this register value that is returned

to the user during an SPI read operation addressed to that DAC

channel. In the special case of a dual channel write to a DAC, both

of the associated X2 registers are sequentially updated using the

appropriate m register and c register for each channel.

When enabled, the calibration function applies this operation to the

X2 registers only after a SPI write to the respective X1 registers.

The X2 registers are not updated after write operations to either m

or range settings of the device. For this reason, to ensure that cali-

bration data is recalculated for any particular DAC, it is necessary

to write fresh data to that DAC after changes are first made to the

associated m register and c register, and any associated functional

modes and ranges for that DAC function.

For each DAC, there is only a single X2 register, and generally

there is one dedicated and unique set of m calibration register

and c calibration register assigned. In several special cases (for

example, the PPMU DAC) there is still only one X2 register per

DAC, but there are several different choices for m register and

c register depending on the particular configuration of mode and

range control settings for the function. For those DACs, a choice of

calibration register is made automatically based on the respective

mode and range control settings in place for that function when the

DAC is written.

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