Nexperia

74HCS30

8-input NAND gate with Schmitt-trigger inputs

4. Functional diagram

B

A

C

D

F

E

G

H

Y

aaa-043592

Fig. 1. Logic diagram

mna488

A

Y

1

8

B

2

C

3

D

4

E

5

F

6

G

11

H

12

Fig. 2. Logic symbol

8

&

mna489

1

2

3

4

5

6

11

12

Fig. 3. IEC logic symbol

5. Pinning information

5.1. Pinning

A

VCC

B

n.c.

C

H

D

G

E

n.c.

F

n.c.

GND

Y

aaa-037234

1

2

3

4

5

6

7

8

10

9

12

11

14

13

D package

SOT108-1 (SO14)

A

VCC

B

n.c.

C

H

D

G

E

n.c.

F

n.c.

GND

Y

aaa-037235

1

2

3

4

5

6

7

8

10

9

12

11

14

13

PW package

SOT402-1 (TSSOP14)

aaa-037236

Transparent top view

F

n.c.

E

n.c.

D

G

C

H

B

n.c.

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

BQ package

SOT762-1 (DHVQFN14)

GND(1)

(1) This is not a ground pin. There is no electrical or mechanical requirement to solder

the pad. In case soldered, the solder land should remain floating or connected to GND.

74HCS30

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© Nexperia B.V. 2025. All rights reserved

Product data sheet

Rev. 1 — 27 June 2025

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