Nexperia

74HCS30

8-input NAND gate with Schmitt-trigger inputs

9.1.2. For outputs

aaa-036301

0

5

10

15

20

25

25

30

35

40

45

50

IOL (mA)

ROL

ROL

(Ω)

(Ω)

(1)

(1)

(2)

(2)

(3)

(3)

(4)

(4)

(5)

(5)

(6)

(6)

(1) VCC = 2.0 V

(2) VCC = 2.5 V

(3) VCC = 3.3 V

(4) VCC = 4.5 V

(5) VCC = 5.0 V

(6) VCC = 6.0 V

Fig. 8. Typical LOW-level output resistance as function

of the output current

aaa-036302

0

5

10

15

20

25

30

38

46

54

62

70

IOH (mA)

ROH

ROH

(Ω)

(Ω)

(1)

(1)

(2)

(2)

(3)

(3)

(4)

(4)

(5)

(5)

(6)

(6)

(1) VCC = 2.0 V

(2) VCC = 2.5 V

(3) VCC = 3.3 V

(4) VCC = 4.5 V

(5) VCC = 5.0 V

(6) VCC = 6.0 V

Fig. 9. Typical HIGH-level output resistance as function

of the output current

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Section 10.1.

25 °C

-40 °C to +85 °C -40 °C to +125 °C

Symbol Parameter Conditions

Min Typ[1] Max

Min

Max

Min

Max

Unit

A, B, C, D, E, F, G, H to Y;

see Fig. 10

[2]

VCC = 2 V

-

22

36

-

42

-

46

ns

VCC = 4.5 V

-

9

22

-

26

-

28

ns

VCC = 6 V

-

8

21

-

25

-

27

ns

VCC = 3.0 V to 3.6 V

-

10

31

-

36

-

40

ns

tpd

propagation

delay

VCC = 4.5 V to 5.5 V

-

8

22

-

26

-

28

ns

nY; see Fig. 10

[3]

VCC = 2 V

-

9

13

-

15

-

16

ns

VCC = 4.5 V

-

5

7

-

8

-

8

ns

VCC = 6 V

-

4

6

-

7

-

7

ns

VCC = 3.0 V to 3.6 V

-

5

8

-

9

-

10

ns

tt

transition

time

VCC = 4.5 V to 5.5 V

-

4

7

-

8

-

8

ns

CI

input

capacitance

-

1.5

-

-

5

-

5

pF

74HCS30

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© Nexperia B.V. 2025. All rights reserved

Product data sheet

Rev. 1 — 27 June 2025

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