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ADSP-CM409F bảng dữ liệu(PDF) 40 Page - Analog Devices |
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ADSP-CM409F bảng dữ liệu(HTML) 40 Page - Analog Devices |
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40 / 124 page  Rev. A | Page 40 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ADSP-CM409F 212-BALL BGA SIGNAL DESCRIPTIONS The processor’s pin definitions are shown in Table 18. The col- umns in this table provide the following information: • Signal Name: The Signal Name column in the table includes the signal name for every pin and (where applica- ble) the GPIO multiplexed pin function for every pin. • Description: The Description column in the table provides a verbose (descriptive) name for the signal. • General-Purpose Port: The Port column in the table shows whether or not the signal is multiplexed with other signals on a general-purpose I/O port pin. • Pin Name: The Pin Name column in the table identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multiplexed (if a general-purpose I/O pin). Table 18. ADSP-CM409F 212-Ball BGA Signal Descriptions Signal Name Description Port Pin Name ADC0_VIN00 Channel 0 Single-Ended Analog Input for ADC0 Not Muxed ADC0_VIN00 ADC0_VIN01 Channel 1 Single-Ended Analog Input for ADC0 Not Muxed ADC0_VIN01 ADC0_VIN02 Channel 2 Single-Ended Analog Input for ADC0 Not Muxed ADC0_VIN02 ADC0_VIN03 Channel 3 Single-Ended Analog Input for ADC0 Not Muxed ADC0_VIN03 ADC0_VIN04 Channel 4 Single-Ended Analog Input for ADC0 Not Muxed ADC0_VIN04 ADC0_VIN05 Channel 5 Single-Ended Analog Input for ADC0 Not Muxed ADC0_VIN05 ADC0_VIN06 Channel 6 Single-Ended Analog Input for ADC0 Not Muxed ADC0_VIN06 ADC0_VIN07 Channel 7 Single-Ended Analog Input for ADC0 Not Muxed ADC0_VIN07 ADC0_VIN08 Channel 8 Single-Ended Analog Input for ADC0 Not Muxed ADC0_VIN08 ADC0_VIN09 Channel 9 Single-Ended Analog Input for ADC0 Not Muxed ADC0_VIN09 ADC0_VIN10 Channel 10 Single-Ended Analog Input for ADC0 Not Muxed ADC0_VIN10 ADC0_VIN11 Channel 11 Single-Ended Analog Input for ADC0 Not Muxed ADC0_VIN11 ADC1_VIN00 Channel 0 Single-Ended Analog Input for ADC1 Not Muxed ADC1_VIN00 ADC1_VIN01 Channel 1 Single-Ended Analog Input for ADC1 Not Muxed ADC1_VIN01 ADC1_VIN02 Channel 2 Single-Ended Analog Input for ADC1 Not Muxed ADC1_VIN02 ADC1_VIN03 Channel 3 Single-Ended Analog Input for ADC1 Not Muxed ADC1_VIN03 ADC1_VIN04 Channel 4 Single-Ended Analog Input for ADC1 Not Muxed ADC1_VIN04 ADC1_VIN05 Channel 5 Single-Ended Analog Input for ADC1 Not Muxed ADC1_VIN05 ADC1_VIN06 Channel 6 Single-Ended Analog Input for ADC1 Not Muxed ADC1_VIN06 ADC1_VIN07 Channel 7 Single-Ended Analog Input for ADC1 Not Muxed ADC1_VIN07 ADC1_VIN08 Channel 8 Single-Ended Analog Input for ADC1 Not Muxed ADC1_VIN08 ADC1_VIN09 Channel 9 Single-Ended Analog Input for ADC1 Not Muxed ADC1_VIN09 ADC1_VIN10 Channel 10 Single-Ended Analog Input for ADC1 Not Muxed ADC1_VIN10 ADC1_VIN11 Channel 11 Single-Ended Analog Input for ADC1 Not Muxed ADC1_VIN11 BYP_A0 On-chip Analog Power Regulation Bypass Filter Node for ADC0 (see recommended bypass -Figure 4 on Page 6) Not Muxed BYP_A0 BYP_A1 On-chip Analog Power Regulation Bypass Filter Node for ADC1 (see recommended bypass - Figure 4 on Page 6) Not Muxed BYP_A1 BYP_D0 On-chip Digital Power Regulation Bypass Filter Node for Analog Subsystem (see recommended bypass - Figure 4 on Page 6) Not Muxed BYP_D0 CAN0_RX CAN0 Receive B PB_15 CAN0_TX CAN0 Transmit C PC_00 CAN1_RX CAN1 Receive B PB_10 CAN1_TX CAN1 Transmit B PB_11 CNT0_DG CNT0 Count Down and Gate B PB_02 CNT0_OUTA CNT0 Output Divider A B PB_13 |
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