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AD5602/AD5612/AD5622

Data Sheet

Rev. E | Page 16 of 23

SERIAL INTERFACE

The AD5602/AD5612/AD5622 have 2-wire I2C compatible

serial interfaces (refer to I2C-Bus Specification, Version 2.1,

January 2000, available from Philips Semiconductor). The

AD5602/AD5612/AD5622 can be connected to an I2C bus as a

slave device, under the control of a master device. See Figure 2

for a timing diagram of a typical write sequence.

The AD5602/AD5612/AD5622 support standard (100 kHz),

fast (400 kHz), and high speed (3.4 MHz) data transfer modes.

Support is not provided for 10-bit addressing and general call

addressing.

The AD5602/AD5612/AD5622 each have a 7-bit slave address.

The five most significant bits (MSB) are 00011 and the two LSBs

are determined by the state of the ADDR pin. The facility to

make hardwired changes to ADDR allows the user to incorporate

up to three of these devices on one bus as outlined in Table 7.

The 2-wire serial bus protocol operates as follows:

The master initiates data transfer by establishing a start

condition, which is when a high to low transition on the

SDA line occurs while SCL is high. The following byte is

the address byte, which consists of the 7-bit slave address.

The slave address corresponding to the transmitted address

responds by pulling SDA low during the ninth clock pulse

(this is termed the acknowledge bit). At this stage, all other

devices on the bus remain idle while the selected device

waits for data to be written to, or read from, its shift register.

Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge

bit). The transitions on the SDA line must occur during the

low period of SCL and remain stable during the high

period of SCL.

When all data bits have been read or written, a stop

condition is established. In write mode, the master pulls

the SDA line high during the 10th clock pulse to establish a

stop condition. If a stop condition is generated between the

7th and 8th clock pulse of the I2C address frame, a power cycle

is required to recover the device. In read mode, the master

issues a no acknowledge for the ninth clock pulse (that is,

the SDA line remains high). The master then brings the

SDA line low before the 10th clock pulse, and then high

during the 10th clock pulse to establish a stop condition.

Table 7. Device Address Selection

ADDR

GND

VDD

NC (No Connection)

INPUT REGISTER

The input register is 16 bits wide. Figure 39, Figure 40, and

Figure 41 illustrate the contents of the input register for each

device. Data is loaded into the device as a 16-bit word under the

control of an SCL input. The timing diagram for this operation

is shown in Figure 2. The 16-bit word consists of four control

bits followed by 8, 10, or 12 bits of data, depending on the device

type. MSB (DB15) is loaded first. The first two bits are reserved

bits that must be set to zero; the next two bits are control bits

that select the mode of operation of the device (normal mode or

any one of three power-down modes). See the Power-Down

Modes section for a complete description. The remaining bits

are left justified DAC data bits, starting with the MSB and

ending with the LSB.

DATA BITS

DB15 (MSB)

DB0 (LSB)

PD1

PD0

Figure 39. AD5602 Input Register Contents

DATA BITS

DB15 (MSB)

DB0 (LSB)

PD1

PD0

Figure 40. AD5612 Input Register Contents

DATA BITS

DB15 (MSB)

DB0 (LSB)

PD1

PD0

D11

D10

Figure 41. AD5622 Input Register Contents

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