EM78P342NP datasheet(35/102 Pages) EMC

35 / 102 page

EM78P341N/342N/343N

8-Bit Microprocessor with OTP ROM

Product Specification (V1.0) 12.01.2006

• 29

(This specification is subject to change without further notice)

6.2.20 IOCD1 (LVD Control Register)

Bit

EM78P342N/343N

LVDIE LVDEN

LVD1

LVD0

ICE342N

TYPE1 TYPE0

LVR1

LVR0

LVDIE LVDEN

LVD1

LVD0

Bits 7~6 (Type 1 ~ Type 0): Type selection for EM78P343N or EM78P342N or

EM78P341N or 108C.

Type 1, Type 0

VDD Reset Level

EM78P343N (Default) (20PIN)

EM78P342N (18PIN)

EM78P341N (14PIN)

108C (8PIN)

Bits 5~4 (LVR1 ~ LVR0): Low Voltage Reset enable bits.

LVR1, LVR0

VDD Reset Level

VDD Release Level

NA (Power-on Reset)

2.7V

2.9V

3.5V

3.7V

4.0V

4.2V

NOTE

■ IOCD1<3> register is both readable and writable

■ Individual interrupt is enabled by setting its associated control bit in the IOCD1 <4> to "1"

■ Global interrupt is enabled by the ENI instruction and is disabled by the DISI

instruction. Refer to Fig. 6-8 (

Interrupt Input Circuit) under Section 6.6 (Interrupt).

Bit 3 (LVDIE): Low voltage Detector interrupt enable bit.

0 = Disable Low voltage Detector interrupt.

1 = Enable Low voltage Detector interrupt.

When the detect low level voltage is used to enter an interrupt vector or

enter next instruction, the LVDIE bit must be set to “Enable“.

Bit 2 (LVDEN):

Low Voltage Detector enable bit

0 = Low voltage detector disable

1 = Low voltage detector enable

Bit 1~0 (LVD1:0): Low Voltage Detector level bits.

LVDEN

LVD1,LVD0

LVD voltage Interrupt level

/LVD

Vdd

≤ 2.3V

Vdd

> 2.3V

Vdd

≤ 3.3V

Vdd

> 3.3V

Vdd

≤ 4.0V

Vdd

> 4.0V

Vdd

≤ 4.5V

Vdd

> 4.5V

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