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IMAGE SENSOR SOLUTIONS
7
Output Structure
Charge packets contained in the horizontal register are
dumped pixel by pixel, onto the floating diffusion output
node whose potential varies linearly with the quantity of
charge in each packet. The amount of potential change is
determined by the expression
∆Vfd=∆Q/Cfd. A three stage
source-follower amplifier is used to buffer this signal
voltage off chip with slightly less than unity gain. The
translation from the charge domain to the voltage domain
is quantified by the output sensitivity or charge to voltage
conversion in terms of µV/e-. After the signal has been
sampled off-chip, the reset clock (øR) removes the charge
from the floating diffusion and resets its potential to the
reset-drain voltage(VRD).
VDD
VOUTA
VSS& OG
VOUTB
HCCDA
HCCDB
RD
φR
VWELL
VSUB
FDB(n/c)
FDA (n/c)
Figure 4 Output Structure
KAI-1010/1011 Rev 8 •
www.k odak.com/go/imagers 585-722- 4385 imagers@kodak.com
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