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KAI-1010M bảng dữ liệu(PDF) 6 Page - List of Unclassifed Manufacturers

tên linh kiện KAI-1010M
Giải thích chi tiết về linh kiện  Image Sensor
PDF  37 Pages
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nhà sản xuất  ETC2 [List of Unclassifed Manufacturers]
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KAI-1010M bảng dữ liệu(HTML) 6 Page - List of Unclassifed Manufacturers

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IMAGE SENSOR SOLUTIONS
6
Charge Transport
The accumulated or integrated charge from each
photodiode is transported to the output by a three step
process. The charge is first transported from the
photodiodes to the VCCDs by applying a large positive
voltage to the phase-one vertical clock (øV1). This reads
out every row, or line, of photodiodes into the VCCDs.
The charge is then transported from the VCCDs to the
HCCDs line by line. Finally, the HCCDs transport these
rows of charge packets to the output structures pixel by
pixel. On each falling edge of the horizontal clock, øH2,
these charge packets are dumped over the output gate
(OG, Figure 4) onto the floating diffusion (FDA and FDB,
Figure 4).
Both the horizontal and vertical shift registers use
traditional two-phase complementary clocking for charge
transport. Transfer to the HCCDs begins when øV2 is
clocked high and then low (while holding øH1A high)
causing charge to be transferred from øV1 to øV2 and
subsequently into the A HCCD. The A register can now
be read out in single line mode. If it is desired to operate
the device in a dual line readout mode for higher frame
rates, this line is transferred into the B HCCD by clocking
øH1A to a low state, and øH1B to a high state while
holding øH2 low. After øH1A is returned to a high state,
the next line can be transferred into the A HCCD. After
this clocking sequence, both HCCDs are read out in
parallel.
The charge capacity of the horizontal CCDs is slightly
more than twice that of the vertical CCDs. This feature
allows the user to perform two-to-one line aggregation in
the charge domain during V-to-H transfer. This device is
also equipped with a fast dump feature that allows the user
to selectively dump complete lines (or rows) of pixels at a
time. This dump, or line clear, is also accomplished during
the V-to-H transfer time by clocking the fast dump gate.
Pixel Pn+1
Pixel Pn
Figure 3 True 2 Phase CCD Cross Section
Direction of Transfer
+V
-V
-V
+V
Q1
Q2
φ
KAI-1010/1011 Rev 8 •
www.k odak.com/go/imagers 585-722- 4385 imagers@kodak.com



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