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PSD934210MIT bảng dữ liệu(PDF) 53 Page - STMicroelectronics

tên linh kiện PSD934210MIT
Giải thích chi tiết về linh kiện  Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM
PDF  89 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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PSD934210MIT bảng dữ liệu(HTML) 53 Page - STMicroelectronics

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PSD834F2V
Figure 27. Port D Structure
Port D – Functionality and Structure
Port D has three I/O pins. See Figure 27 and Fig-
ure 28. This port does not support Address Out
mode, and therefore no Control Register is re-
quired. Port D can be configured to perform one or
more of the following functions:
s
MCU I/O Mode
s
CPLD Output – External Chip Select (ECS0-
ECS2)
s
CPLD Input – direct input to the CPLD, no Input
Macrocells (IMC)
s
Slew rate – pins can be set up for fast slew rate
Port D pins can be configured in PSDsoft Express
as input pins for other dedicated functions:
s
Address Strobe (ALE/AS, PD0)
s
CLKIN (PD1) as input to the macrocells flip-
flops and APD counter
s
PSD Chip Select Input (CSI, PD2). Driving this
signal High disables the Flash memory, SRAM
and CSIOP.
External Chip Select
The CPLD also provides three External Chip Se-
lect (ECS0-ECS2) outputs on Port D pins that can
be used to select external devices. Each External
Chip Select (ECS0-ECS2) consists of one product
term that can be configured active High or Low.
The output enable of the pin is controlled by either
the output enable product term or the Direction
Register. (See Figure 28.)
DATA OUT
REG.
DQ
DQ
WR
WR
ECS[ 2: 0]
READ MUX
P
D
B
CPLD - INPUT
DIR REG.
DATA IN
ENABLE PRODUCT
TERM (.OE)
OUTPUT
SELECT
OUTPUT
MUX
PORT D PIN
DATA OUT
AI02889



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