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PSD934210MIT bảng dữ liệu(PDF) 46 Page - STMicroelectronics

tên linh kiện PSD934210MIT
Giải thích chi tiết về linh kiện  Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM
PDF  89 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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PSD934210MIT bảng dữ liệu(HTML) 46 Page - STMicroelectronics

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Table 18. Port Operating Modes
Note: 1. Can be multiplexed with other I/O functions.
Table 19. Port Operating Mode Settings
Note: 1. N/A = Not Applicable
2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
3. Any of these three methods enables the JTAG pins on Port C.
Port Mode
Port A
Port B
Port C
Port D
MCU I/O
Yes
Yes
Yes
Yes
PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs
PLD Inputs
Yes
No
No
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
No
Yes
Yes
Address Out
Yes (A7 – 0)
Yes (A7 – 0)
or (A15 – 8)
No
No
Address In
Yes
Yes
Yes
Yes
Data Port
Yes (D7 – 0)
No
No
No
Peripheral I/O
Yes
No
No
No
JTAG ISP
No
No
Yes1
No
Mode
Defined in
PSDabel
Defined in PSD
Configuration
Control
Register
Setting
Direction
Register
Setting
VM
Register
Setting
JTAG Enable
MCU I/O
Declare pins only
N/A1
0
1 = output,
0 = input
(Note 2)
N/A
N/A
PLD I/O
Logic equations
N/A
N/A
(Note 2)
N/A
N/A
Data Port (Port A)
N/A
Specify bus type
N/A
N/A
N/A
N/A
Address Out
(Port A,B)
Declare pins only
N/A
1
1 (Note 2)
N/A
N/A
Address In
(Port A,B,C,D)
Logic for equation
Input Macrocells
N/A
N/A
N/A
N/A
N/A
Peripheral I/O
(Port A)
Logic equations
(PSEL0 & 1)
N/A
N/A
N/A
PIO bit = 1
N/A
JTAG ISP (Note 3)
JTAGSEL
JTAG
Configuration
N/A
N/A
N/A
JTAG_Enable



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