PIC16F877 datasheet(5/22 Pages) MICROCHIP

5 / 22 page

 2002 Microchip Technology Inc.

DS39025F-page 5

PIC16F87X

2.4

Program/Verify Mode

The Program/Verify mode is entered by holding pins

RB6 and RB7 low, while raising MCLR pin from VIL to

VIHH (high voltage). In this mode, the state of the RB3

pin does not effect programming. Low voltage ICSP

Programming mode is entered by raising RB3 from VIL

to VDD and then applying VDD to MCLR. Once in this

mode, the user program memory and the configuration

memory can be accessed and programmed in serial

fashion. The mode of operation is serial, and the mem-

ory that is accessed is the user program memory. RB6

and RB7 are Schmitt Trigger Inputs in this mode.

The sequence that enters the device into the Program-

ming/Verify mode places all other logic into the RESET

state (the MCLR pin was initially at VIL). This means

that all I/O are in the RESET state (high impedance

inputs).

The normal sequence for programming is to use the

load data command to set a value to be written at the

selected address. Issue the begin programming com-

mand followed by read data command to verify, and

then increment the address.

A device RESET will clear the PC and set the address

to 0. The “increment address” command will increment

the PC. The “load configuration” command will set the

PC to 0x2000. The available commands are shown in

Table 2-2.

2.4.1

LOW VOLTAGE ICSP

PROGRAMMING MODE

Low voltage ICSP Programming mode allows a

PIC16F87X device to be programmed using VDD only.

However, when this mode is enabled by a configuration

bit (LVP), the PIC16F87X device dedicates RB3 to

control entry/exit into Programming mode.

When LVP bit is set to ‘1’, the low voltage ICSP pro-

gramming entry is enabled. Since the LVP configura-

tion bit allows low voltage ICSP programming entry in

its erased state, an erased device will have the LVP bit

enabled at the factory. While LVP is ‘1’, RB3 is dedi-

cated to low voltage ICSP programming. Bring RB3 to

VDD and then MCLR to VDD to enter programming

mode. All other specifications for high voltage ICSP™

apply.

To disable low voltage ICSP mode, the LVP bit must be

programmed to ‘0’. This must be done while entered

with High Voltage Entry mode (LVP bit = 1). RB3 is now

a general purpose I/O pin.

2.4.2

SERIAL PROGRAM/VERIFY

OPERATION

The RB6 pin is used as a clock input pin, and the RB7

pin is used for entering command bits and data

input/output during serial operation. To input a com-

mand, the clock pin (RB6) is cycled six times. Each

command bit is latched on the falling edge of the clock,

with the Least Significant bit (LSb) of the command

being input first. The data on pin RB7 is required to

have a minimum setup and hold time (see AC/DC

specifications), with respect to the falling edge of the

clock. Commands that have data associated with them

(read and load) are specified to have a minimum delay

of 1

µs between the command and the data. After this

delay, the clock pin is cycled 16 times with the first cycle

being a START bit and the last cycle being a STOP bit.

Data is also input and output LSb first.

Therefore, during a read operation, the LSb will be

transmitted onto pin RB7 on the rising edge of the sec-

ond cycle, and during a load operation, the LSb will be

latched on the falling edge of the second cycle. A min-

imum 1

µs delay is also specified between consecutive

commands.

All commands are transmitted LSb first. Data words are

also transmitted LSb first. The data is transmitted on

the rising edge and latched on the falling edge of the

clock. To allow for decoding of commands and reversal

of data pin configuration, a time separation of at least

µs is required between a command and a data word

(or another command).

The commands that are available are:

2.4.2.1

Load Configuration

After receiving this command, the program counter

(PC) will be set to 0x2000. By then applying 16 cycles

to the clock pin, the chip will load 14-bits in a “data

word,” as described above, to be programmed into the

configuration memory. A description of the memory

mapping schemes of the program memory for normal

operation and Configuration mode operation is shown

in Figure 2-1. After the configuration memory is

entered, the only way to get back to the user program

memory is to exit the Program/Verify Test mode by

taking MCLR low (VIL).

2.4.2.2

Load Data for Program Memory

After receiving this command, the chip will load in a

14-bit “data word” when 16 cycles are applied, as

described previously. A timing diagram for the load data

command is shown in Figure 6-1.

Note:

The OSC must not have 72 osc clocks

while the device MCLR is between VIL and

VIHH.

PIC16F877 bảng dữ liệu(PDF) 5 Page - Microchip Technology

PIC16F877 bảng dữ liệu(HTML) 5 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

bảng dữ liệu tải về

Link URL