PSD935G2 datasheet(76/91 Pages) STMICROELECTRONICS

tên linh kiện	PSD935G2

Giải thích chi tiết về linh kiện	Configurable Memory System on a Chip for 8-Bit Microcontrollers

PDF	91 Pages

Scroll/Zoom	100%

nhà sản xuất	STMICROELECTRONICS [STMicroelectronics]

Trang chủ	http://www.st.com

Logo

76 / 91 page

PSD935G2

PSD9XX Family

-90

-12

Turbo

Symbol

Parameter

Conditions

Min

Max

Min

Max

Off

Unit

tLVLX

ALE or AS Pulse Width

tAVLX

Address Setup Time

(Note 3)

tLXAX

Address Hold Time

(Note 3)

tAVQV

Address Valid to Data Valid

(Note 3)

120

Add 20**

t SLQV

CS Valid to Data Valid

120

RD to Data Valid

(Note 5)

t RLQV

RD or PSEN to Data Valid,

80C51 Mode

(Note 2)

t RHQX

RD Data Hold Time

(Note 1)

tRLRH

RD Pulse Width

(Note 1)

tRHQZ

RD to Data High-Z

(Note 1)

tEHEL

E Pulse Width

tTHEH

R/W Setup Time to Enable

tELTL

R/W Hold Time After Enable

tAVPV

Address Input Valid to

(Note 4)

Address Output Delay

Read Timing (3.0 V to 3.6 V Versions)

Microcontroller Interface – PSD935G2 AC/DC Parameters

(3.0 V to 3.6 V Versions)

NOTES: 1. RD timing has the same timing as DS and PSEN signals.

2. RD and PSEN have the same timing for 80C51.

3. Any input used to select an internal PSD4135G2V function.

4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.

5. RD timing has the same timing as DS signals.

PSD935G2 bảng dữ liệu(PDF) 76 Page - STMicroelectronics

PSD935G2 bảng dữ liệu(HTML) 76 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

bảng dữ liệu tải về

Link URL