PSD935G2 datasheet(71/91 Pages) STMICROELECTRONICS

71 / 91 page

PSD9XX Family

PSD935G2

-70

-90

Symbol

Parameter

Conditions

Min

Max

Min

Max

Unit

tLVLX

ALE or AS Pulse Width

tAVLX

Address Setup Time

(Note 1)

tLXAX

Address Hold Time

(Note 1)

tAVWL

Address Valid to Leading

Edge of WR

(Notes 1 and 3)

t SLWL

CS Valid to Leading Edge of WR

(Note 3)

t DVWH

WR Data Setup Time

(Note 3)

t WHDX

WR Data Hold Time

(Note 3)

t WLWH

WR Pulse Width

(Note 3)

tWHAX1

Trailing Edge of WR to Address

Invalid

(Note 3)

tWHAX2

Trailing Edge of WR to DPLD

Address Input Invalid

(Note 3 and 4)

tWHPV

Trailing Edge of WR to Port Output

Valid Using I/O Port Data Register

(Note 3)

tAVPV

Address Input Valid to Address

(Note 2)

Output Delay

Write Timing (5 V ± 10% Versions)

NOTES: 1.

Any input used to select an internal PSD935G2 function.

In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.

WR timing has the same timing as E, DS signals.

tWHAX2 is Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.

Microcontroller Interface – PSD935G2 AC/DC Parameters

(5V ± 10% Versions)

-70

-90

Slew

TURBO

Rate

Symbol

Parameter

Conditions

Min

Max

Min

Max

OFF

(Note 1)

Unit

tPD

PLD Input Pin/Feedback to

Add 12

Sub 2

PLD Combinatorial Output

tARD

PLD Array Delay

PLD Combinatorial Timing (5 V ± 10%)

NOTE: 1. Fast Slew Rate output available on Port C and F.

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