MB91F313 datasheet(21/71 Pages) FUJITSU

21 / 71 page

MB91313 Series

■ RESTRICTIONS

1) Clock control block

When an “L” level is input to the INITX pin, ensure that it is maintained for the duration of the oscillation

stabilization wait time.

2) Bit Search Module

The bit search data register for 0-detection (BSD0), bit search data register for 1-detection (BSD1), and bit

search data register for change point detection (BSDC) can be accessed in word.

3) I/O Ports

Ports can only be accessed in byte.

4) Low Power Consumption Mode

• To place the device in standby mode, use the synchronous standby mode (set with bit 8 (SYNCS bit) of the

timebase counter control register, TBCR) and be sure to use the following sequence :

(LDI#value_of_standby, r0) ; value_of_standby is the data to write to STCR

(LDI#_STCR, R12)

; _STCR is the address of STCR (481H)

STB

R0, @R12

; Write to the standby control register (STCR)

LDUB

@R12, R0

; Read STCR for synchronous standby

LDUB

@R12, R0

; Perform an additional dummy read of STCR

NOP

; 5

× NOP for timing adjustment

NOP

• Do not perform any of the following actions when using the monitor debugger.

• Set a breakpoint within the sequence of instructions shown above

• Perform step execution of the sequence of instructions shown above

MB91F313 bảng dữ liệu(PDF) 21 Page - fujitsu semiconductor