MB91F313 datasheet(2/71 Pages) FUJITSU

2 / 71 page

MB91313 Series

• On-chip multiplier supported at the instruction level

- Signed 32-bit multiplication : 5 cycles

- Signed 16-bit multiplication : 3 cycles

• Interrupt (PC, PS save) : 6 cycles, 16 priority levels

• Harvard architecture enabling program access and data access to be executed simultaneously

• Instruction prefetch feature implemented using a 4-word queue in the CPU

• Instruction compatible with the FR family

Simple External Bus Interface

• Function as an 8-bit or 16-bit multiplexed bus through programmatic settings

• Operating frequency : Max 16.5 MHz

• Multiplexed I/O for 8/16-bit data/address

• Capable of chip-select signal output for 4 completely independent areas configurable in minimum units of

64 Kbytes

• Basic bus cycle : 3 cycles

• Automatic wait cycle generation function to be programmed for each area

• Unused data/address/control signal pins can serve as general-purpose I/O

Built-in Memory

Flash : 544 Kbytes, RAM : 32 Kbytes

DMAC (DMA Controller)

• 5 channels

• Two transfer sources : Internal peripheral/software

• Addressing modes : 20/24-bit address selectable (increment/decrement/fixed)

• Transfer modes : Burst transfer/step transfer/block transfer

• Transfer data size : Selectable from 8, 16, or 32 bits

Bit Search Module (for REALOS)

Function to search from the MSB (most significant bit) for the position of the first “0”, “1”, or changed bit in a

word

16-bit Reload Timer (Including 1 Channel for REALOS)

• 6 channels

• Internal clock: Frequency division selectable from 2, 8, and 32

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