PSD4235G2 datasheet(45/89 Pages) STMICROELECTRONICS

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PSD4235G2

Figure 23. Interfacing the PSD with an 80C51XA-G3

80C51XA. The Philips 80C51XA MCU has a 16-

bit multiplexed bus with burst cycles. Address bits

(A3-A1) are not multiplexed, while (A19-A4) are

multiplexed with data bits (D15-D0).

The PSD4235G2 supports the 80C51XA burst

mode. The WRH signal is connected to PD3, and

WHL is connected to CNTL0. The RD and PSEN

signals are connected to the CNTL1 and CNTL2

pins. Figure 23 shows the schematic diagram.

The 80C51XA improves bus throughput and per-

formance by issuing burst cycles to fetch codes

from memory. In burst cycles, address A19-A4 are

latched internally by the PSD, while the 80C51XA

drives the A3-A1 signals to fetch sequentially up to

16 bytes of code. The PSD access time is then

measured from address A3-A1 valid to data in val-

id. The PSD bus timing requirement in a burst cy-

cle is identical to the normal bus cycle, except the

address setup and hold time with respect to Ad-

dress Strobe (ALE/AS, PD0) is not required.

VCC_BAR

D[15:0]

WRL\

RD\

PSEN\

ALE

A4D0

A5D1

A6D2

A7D3

A8D4

A9D5

A10D6

A11D7

A12D8

A13D9

A14D10

A15D11

A16D12

A17D13

A18D14

A19D15

RESET\

WRH\

A[3:1]

CRYSTAL

PSD

ADIO0

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

ADIO9

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PA5

PA6

PA7

CNTL0(WR)

CNTL1(RD)

CNTL2(PSEN)

PD0 (ALE)

RESET

ADIO8

PG0

PA3

PA4

PA2

PA0

PA1

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PE0 (TMS)

PE1 (TCK/ST)

PE2 (TDI)

PE3 (TDO)

PE4 (TSTAT/RDY)

PE5 (TERR)

PE7 (VBATON)

PD2 (CSI)

PD1 (CLKIN)

PD3 (WRH)

PE6 (VSTBY)

XA-G3

A0/WRH

A4D0

A5D1

A6D2

A7D3

A8D4

A9D5

A10D6

A11D7

A12D8

A13D9

A14D10

A15D11

A16D12

A17D13

A18D14

A19D15

PSEN

WRL

ALE

RST

INT0

INT1

EA/WAIT

BUSW

XTAL1

XTAL2

RXD0

TXD0

RXD1

TXD1

T2EX

D[15:0]

A[3:1]

AI04952b

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