MK50H28 datasheet(39/64 Pages) STMICROELECTRONICS

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BIT

NAME

DESCRIPTION

OWNA

When this bit is a zero the HOST owns this descriptor. When this bit is a one the

MK50H28 owns this descriptor. The chip clears the OWNA bit after filling the buffer

pointed to by the descriptor entry provided a valid frame has been received. The Host

sets the OWNA bit after emptying the buffer. Once the MK50H28 or the Host has

relinquished ownership of a buffer, it may not change any field in the four words that

comprise the descriptor entry.

EOR

End Of Ring. This bit is set by the host to indicate that this is the last descriptor in the

ring.

C/R

Command/Response Indication Bit. This bit equals the state of the C/R bit for the

received frame.

ELF

End of Long Frame indicates that this is the last buffer used by the MK50H28 for this

frame. ELF is used for data chaining buffers and is set by the MK50H28. ELF=0

indicates that this buffer is one in a chain. When not chaining, ELF will always be one.

FECN

Forward Explicit Congestion Notification Bit. This bit equals the state of the FECN bit for

the received frame.

BECN

Backward Explicit Congestion Notification Bit. This bit equals the state of the BECN bit for

the received frame.

Discard Eligibility Bit. This bit equals the state of the DE bit for the received frame.

FRER

Frame in Error Bit. This bit is valid only if RBFRS is set in CTADR+12. This bit will be set

by the MK50H28 only if an aborted or a bad FCS frame is received.

07:00

RBADR

The High Order 8 address bits of the buffer pointed to by this descriptor. This field is

written by the Host and unchanged by MK50H28.

4.3.1 Receive Message Descriptor Entry

4.3.1.1 Receive Message Descriptor 0 (RMD0) For Non-LMI Channel

RBADR<23:16>

C/R

4.3.1.2 Receive Message Descriptor 0 (RMD0) For LMI Channel

RBADR<23:16>

Frame

Type

BIT

NAME

DESCRIPTION

OWNA

When this bit is a zero, the HOST owns this descriptor. When this bit is a one the

MK50H28 owns this descriptor. The chip clears the OWNA bit after filling the buffer

pointed to by the descriptor entry, provided a valid frame has been received. The Host

should set the OWNA bit after emptying the buffer. Once the MK50H28 or Host

relinquishes ownership of a buffer, it may not change any field in the descriptor entry.

MK50H28

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