R5F5671CDDFM datasheet(155/179 Pages) RENESAS

155 / 179 page

R01DS0373EJ0120 Rev.1.20

Page 155 of 179

Sep 30, 2024

RX671 Group

2. Electrical Characteristics

2.6

A/D Conversion Characteristics

Note:

The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds

during A/D conversion, values may not fall within the above ranges.

Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states

is indicated.

Note 2. The value in parentheses indicates the sampling time.

Note:

The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds

during A/D conversion, values may not fall within the above ranges.

Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states

is indicated.

Note 2. The value in parentheses indicates the sampling time.

Table 2.53

12-Bit A/D (Unit 0) Conversion Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKB = PCLKC = 1 MHz to 60 MHz, Ta = Topr,

Source impedance = 1.0 kΩ

Item

Min.

Typ.

Max.

Unit

Test Conditions

Resolution

—

Bit

Analog input capacitance

—

Conversion time*1

(Operation at PCLKC = 60 MHz)

0.48

(0.267)*2

—

µs

Sampling in 16 states

Offset error

—

±1.0

±2.5

LSB

Full-scale error

—

±1.0

±2.5

LSB

Quantization error

—

±0.5

—

LSB

Absolute accuracy

—

±2.5

±4.5

LSB

DNL differential nonlinearity error

—

±0.5

±1.5

LSB

INL integral nonlinearity error

—

±1.0

±2.5

LSB

Table 2.54

12-Bit A/D (Unit 1) Conversion Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKB = PCLKD = 1 MHz to 60 MHz, Ta = Topr,

Source impedance = 1.0 kΩ

Item

Min.

Typ.

Max.

Unit

Test Conditions

Resolution

—

Bit

Conversion time*1

(Operation at PCLKD = 60 MHz)

0.88

(0.633)*2

—

µs

Sampling in 38 states

(ADSAM.SAM = 1)

Conversion time*1

(Operation at PCLKD = 30 MHz)

(0.500)*2

—

µs

Sampling in 15 states

(ADSAM.SAM = 1)

Analog input capacitance

—

Offset error

—

±2.0

±3.5

LSB

Full-scale error

—

±2.0

±3.5

LSB

Quantization error

—

±0.5

—

LSB

Absolute accuracy

—

±4.0

±6.0

LSB

DNL differential nonlinearity error

(Operation at PCLKD = 60 MHz)

—

±1.5

±4.0

LSB

DNL differential nonlinearity error

(Operation at PCLKD = 30 MHz)

—

±1.5

±2.5

LSB

INL integral nonlinearity error

(Operation at PCLKD = 60 MHz)

—

±2.0

±4.0

LSB

INL integral nonlinearity error

(Operation at PCLKD = 30 MHz)

—

±2.0

±3.5

LSB

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