RZSLASHA1M datasheet(5/137 Pages) RENESAS

5 / 137 page

R01DS0479EJ0100 Rev.1.00

Page 5 of 137

Dec. 25, 2024

RZ/A1H Group, RZ/A1M Group

1. Overview

LIN interface

 Two channels

 Conforms with revisions 1.3, 2.0, 2.1, and 2.2 of the LIN protocol and SAEJ 2062.

 Master mode supported

Ethernet controller

 Conforms with the Ethernet or the IEEE802.3 MAC (Media Access Control) layer standard

 MAC function

Constructs/deconstructs data frames (frame format conforming to IEEE802.3, 2000 Edition)

Supports transfer at 10 and 100 Mbps

Supports full-duplex mode

Flow control conforming to IEEE802.3x

Supports an MII (Media Independent Interface) for connection to a PHY interface in conformance

with IEEE 802.3

Upward protocol support (checksum) function

 E-DMAC (Direct Memory Access Controller for Ethernet controller) function

EthernetAVB

 Conforms with the Ethernet or the IEEE802.3 MAC (Media Access Control) layer standard

 MAC function

Constructs/deconstructs data frames (frame format conforming to IEEE802.3, 2000 Edition)

Supports transfer at 100 Mbps

Supports full-duplex mode

Flow control conforming to IEEE802.3x

Supports an MII (Media Independent Interface) for connection to a PHY interface in conformance

with IEEE 802.3

Upward protocol support (checksum) function

 AVB-DMAC (DMAC dedicated to EthernetAVB) function

AVB-DMAC conforms with the following 3 standards; IEEE802.1AS (Clock Synchronization

Protocol), IEEE802.1Qav (Realtime Transfer Protocol) and IEEE802.1Qat (Bandwidth Reservation

Protocol)

NAND flash memory

controller

 Direct-connected memory interface with NAND-type flash memory

 Command access mode

 Interrupt request and DMA transfer request

 Supports flash memory requiring 5-byte addresses (2 Gbits and more)

USB 2.0 host/function module

 Two channels

 Conforms to the Universal Serial Bus Specification Revision 2.0

 480-Mbps, 12-Mbps, and 1.5-Mbps transfer rates provided (host mode)

 480-Mbps and 12-Mbps transfer rates provided (function mode)

 On-chip 8-Kbyte RAM as communication buffers

Digital video decoder

 Two channels

 Video input

Composite video input (CVBS)

 A/D converter for video signal input

VIN1 and VIN2 pin input selection

Low-pass filter (LPF)

Sync tip clamp

Programmable gain amplifier (PGA) (0 to 6.021 dB)

10-bit precision pipelined A/D converter

 Sync separation

Noise reduction LPF, auto level control sync slicer, horizontal auto frequency control (AFC), vertical

count-down, interlace detection, auto gain control (AGC)/peak limiter control

 Y/C separation

NTSC 2D, PAL 2D, and SECAM 1D supported.

 Chroma-key decoding

NTSC, PAL, and SECAM supported.

Color killer, auto color control (ACC), TINT correction, R-Y axis correction

 Digital clamp

Pedestal clamp (Y), center clamp (Cb/Cr), noise detection

 Adjustment of output gain

Contrast: 0 to approximately 2 times

Color (Cb/Cr independently): 0 to approximately 2 times

Items

Specification

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