RZSLASHG2UL datasheet(55/67 Pages) RENESAS

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RZ/G2UL Group

3. Electrical Characteristics

R01DS0486EJ0110 Rev.1.10

Page 55 of 67

Jun 16, 2025

3.5.15

Serial Communications Interface with FIFO (SCIFA) Access Timing

Table 3.42

SCIFA Timing

Item

Symbol

Min.

Max.

Unit

Figures

SCIFA

Input clock cycle

Asynchronous

tScyc

—

tp1cyc*1

Figure 3.41

Clocked

synchronous

—

Input clock pulse width

tSCKW

0.4

0.6

tp1cyc*1

Input clock rise time

tSCKr

—

Input clock fall time

tSCKf

—

Output clock cycle

Asynchronous*2

tScyc

—

tp1cyc*1

Clocked

synchronous

—

Output clock pulse width

tSCKW

0.4

0.6

tp1cyc*1

Output clock rise time

tSCKr

—

Output clock fall time

tSCKf

—

Transmit data delay time

Internal clock

tTXD

−10

Figure 3.42

External clock

3 × tp1cyc*1 4 × tp1cyc*1

+ 20

Receive data setup time

Internal clock

tRXS

3 × tp1cyc*1

+ 20

—

External clock

tp1cyc*1 +

—

Receive data hold time

Internal clock

tRXH

−3 ×

tp1cyc*1

—

External clock

2 × tp1cyc*1

+ 10

—

Note: AC access timing condition: drive ability 12mA, output load 30pF, slew rate = fast

Note 1.

tp1cyc indicates peripheral clock means SCIFn_CLK_PCK (P0ϕ) (n = 0 to 4).

Note 2.

When the SEMR.ABCS0 and SEMR.BGDM bits are set to 1.

SCIFn_SCK

(n = 0 to 4)

tSCKW

tScyc

tSCKr

tSCKf

Figure 3.41

SCK Input Clock Timing

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