R5F51406ADFN datasheet(2/121 Pages) RENESAS

2 / 121 page

R01DS0379EJ0120 Rev.1.20

Page 2 of 121

Nov 22, 2024

RX140 Group

1. Overview

Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different

packages.

Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will

differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different

Packages in the RX140 Group.

Table 1.1

Outline of Specifications (1/4)

Classification

Module/Function

Description

CPU

 Maximum operating frequency: 48 MHz

 32-bit RX CPU (RX v2)

 Minimum instruction execution time: One instruction per clock cycle

 Address space: 4-Gbyte linear

 Register set

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

 Basic instructions: 75 (variable-length instruction format)

 Floating point instructions: 11

 DSP instructions: 23

 Addressing modes: 11

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit

 On-chip divider: 32-bit ÷ 32-bit → 32 bits

 Barrel shifter: 32 bits

FPU

 Single precision (32-bit) floating point

 Data types and exceptions in conformance with the IEEE754 standard

Memory

ROM

 Capacity: 64 K/128 K/256 Kbytes

 32 MHz ≤: No-wait cycle access

 32 MHz to 48 MHz: One-wait cycle access

 Programming/erasing method:

Serial programming (asynchronous serial communication), self-programming

RAM

 Capacity: 16 K/32 K/64 Kbytes

 No-wait memory access

E2 DataFlash

 Capacity: 4 K/8 Kbytes

 Number of erase/write cycles: 1,000,000 (typ.)

MCU operating mode

Single-chip mode

Clock

Clock generation circuit

 Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,

PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator

 Oscillation stop detection: Available

 Clock frequency accuracy measurement circuit (CAC)

 Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock

(FCLK)

The CPU and system sections such as other bus masters run in synchronization with the system

clock (ICLK): 48 MHz (at max.)

Peripheral modules run in synchronization with the PCLKB: 32 MHz (at max.)

The flash peripheral circuit runs in synchronization with the FCLK: 48 MHz (at max.)

 ADCLK in the S12AD runs in synchronization with PCLKD: Up to 48 MHz

 The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16, 32,

64)

Resets

RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and

software reset

Voltage detection

Voltage detection circuit

(LVDAb)

 When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt

is generated.

Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels

Voltage detection circuit 1 is capable of selecting the detection voltage from 14 levels

Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels

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